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(parent: c58d9f2) | patch
Nested VMX: Flush TLBs and Caches if paging mode changed
authorYang Zhang <yang.z.zhang@Intel.com>
Tue, 6 Aug 2013 15:22:35 +0000 (17:22 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 6 Aug 2013 15:22:35 +0000 (17:22 +0200)
commite1ab5c77b44b7bd835a2c032fa4963b36545fdb3
tree69a4dd9d1b28b3dc86ed0b977a334a0c70927467tree | snapshot
parentc58d9f2f4844c2ce8859a8d0f26a54cd058eb51fcommit | diff
Nested VMX: Flush TLBs and Caches if paging mode changed

According to SDM, if paging mode is changed, then whole TLBs and caches will
be flushed. This is missed in nested handle logic. Also this fixed the issue
that 64 bits windows cannot boot up on top of L1 kvm.

Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Acked-by: Keir Fraser <keir@xen.org>
xen/arch/x86/mm/paging.c diff | blob | history
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